The introduction of copper (Cu) metal into multilayer metallization schemes for manufacturing integrated circuits necessitates the use of barrier layers to promote adhesion and growth of the Cu layers and to prevent diffusion of Cu into dielectric materials, for example low dielectric constant (low-k) dielectric materials with k values below that of SiO2 (k˜3.9). Barrier layers that are deposited onto dielectric materials can include refractive materials, such as tungsten (W), molybdenum (Mo), and tantalum (Ta), and compounds thereof. These materials are non-reactive and immiscible in Cu, and can offer low electrical resistivity.
Cu integration schemes for technology nodes less than or equal to 130 nm can utilize a Ta-containing barrier layer, e.g., Ta, TaN, or a combination thereof. The presence of impurities in the Ta-containing barrier layer can result in poor adhesion between the Ta-containing barrier layer and adjacent materials, including Cu metal layers. The impurities can include reaction by-products from partially reacted Ta-precursors in the Ta-containing barrier layer, or oxidation of the Ta-containing barrier layer during deposition of the barrier layer, during transfer of the barrier layer between processing chambers, or during air exposure of the barrier layer in a manufacturing process flow. The poor adhesion between the Ta-containing barrier layer and adjacent materials can result in electro-migration (EM) and stress migration (SM) problems in the integrated circuit, as well as reduced device production yields.
Conventional plasma etching (cleaning) processes for removing impurities from substrates and barrier layers include processes that can cause plasma damage of the substrates and the barrier layers due to high kinetic energies of ions impinging on the substrate or the barrier layers. In many cases these plasma etching processes can cause at least partial removal of the diffusion barrier layers. As the minimum feature sizes of microelectronic devices in integrated circuits are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits, the miniaturization necessitates the use of ultra-thin barrier layers, often with a thickness of only a few nanometers (nm). Therefore, even partial removal of a thickness of an ultra-thin diffusion barrier layer using common plasma etching processes is not acceptable.
Therefore, new dry cleaning processes are needed for cleaning of oxidized surface layers in integrated circuits, including cleaning of oxidized surface layers of ultra-thin barriers layers in advanced metallization schemes.